10 AMD Software Engineer (New Grad) Interview Questions (2026)

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STAR: pick a real debugging story with concrete tools (gdb, perf, profiler, logs). Walk through your hypothesis → narrow → fix. AMD interviewers value methodical thinking — show your debug tree, not luck. End with what you put in place to prevent recurrence.

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Tie to a specific division — GPU drivers (Radeon/Instinct), ROCm AI stack, CPU performance tooling, firmware, or datacenter solutions. Show you understand AMD's recent growth in datacenter GPU (MI300X, MI355X) and what that means for software hiring. Avoid 'I want to work at a chip company'.

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Pick a real example — an internship project, an open-source contribution, etc. Show your learning process: starting with build + run, reading the smallest end-to-end path, asking targeted questions. End with what you shipped.

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Binary search between 0 and n. For each mid, square it and compare to n. Walk through overflow handling (mid * mid can overflow 32-bit). O(log n) time, O(1) space. Newton's method is an alternative with faster convergence; mention it.

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Walk the matrix returning matrix[i][j] where i + j == k. Bounded by matrix dimensions. Discuss row-major vs. column-major traversal and cache friendliness — this often shows up as a follow-up at AMD.

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DP: lis[i] = 1 + max(lis[j]) for j < i where arr[j] < arr[i]. O(n^2) time, O(n) space. Optimal: binary-search version with a tails array, O(n log n) time. Walk through both, code one (most interviewers accept the DP).

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C++11+ guarantees thread-safe initialization of static local variables, so the canonical pattern is: static Instance& get() { static Instance instance; return instance; }. Walk through why this is correct (Meyers' singleton). For older C++, use double-checked locking with std::atomic. Discuss memory order.

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SIMD (Single Instruction Multiple Data) — one instruction operates on a vector register; explicit in code. SIMT (Single Instruction Multiple Threads) — many threads run the same instruction in lockstep (a 'warp' or 'wave'); each thread has its own registers. Mention divergence cost (when threads in a warp take different paths) and how driver code minimizes it.

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Preemptive: OS forcibly suspends a running task at scheduler tick; safer, fairer, but higher context-switch cost. Cooperative: tasks must yield voluntarily; cheaper switches but a misbehaving task starves others. Modern OSes use preemptive for OS threads, cooperative for fibers/coroutines in user-space schedulers.

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Write-through: write goes to both cache and main memory immediately. Simpler, slower, easier coherence. Write-back: write only updates the cache; main memory updates on eviction. Faster but more complex coherence (dirty bit). Most modern CPUs use write-back.