Physical Design Engineer (Place & Route)

About this role

Astera Labs seeks an experienced Physical Design Engineer to lead place-and-route efforts for advanced connectivity ASICs serving major cloud providers. This generalist role spans floorplanning, timing closure, and physical sign-off, guiding designs from RTL through production at 7nm and below technologies.

What you'll do

• Execute place-and-route and timing closure for complex SoC designs targeting production
• Manage block-level ownership from architecture through GDSII handoff
• Collaborate with design, verification, and operations teams on connectivity ASIC projects
• Develop and maintain timing constraints and signoff methodologies
• Interface with IP vendors on RTL and hard-macro block integration
• Support physical design sign-off including extraction, EM-IR, and formal verification

What they're looking for

• Place and route (P&R) tools (Cadence, Synopsys)
• Timing analysis and closure
• Synthesis and backend design flows
• SystemVerilog/Verilog
• Tcl, Python, or Perl scripting
• 7nm or advanced node technologies
• EM-IR analysis and power delivery
• Formal equivalence verification

Benefits

• Competitive base salary: $160K–$195K (Staff) or $203K–$230K (Principal)
• Equity compensation
• Work on cutting-edge AI infrastructure connectivity solutions
• On-site position in San Jose, California
• Collaborative environment with hyperscaler and OEM partners