Astera Labs
Principle Design Verification Engineer SerDes/PHY
San Jose, California, United States$207k–$230kmidAdded today
About this role
Astera Labs seeks a Principal Design Verification Engineer to lead the functional verification of high-speed SerDes/PHY IP crucial for AI infrastructure. This hands-on role involves collaborating with various teams and utilizing advanced verification techniques to ensure silicon success in next-generation AI systems.
What you'll do
- Architect UVM-based verification environments for SerDes/PHY IP
- Define verification plans and coverage models for high-speed serial link blocks
- Drive methodology decisions for co-simulation and emulation flows
- Develop SystemVerilog/UVM testbenches and sequences
- Execute functional and performance verification across various scenarios
- Mentor junior engineers and collaborate with cross-functional teams
What they're looking for
- Expertise in verification methodologies
- Proficiency in SystemVerilog and UVM
- Understanding of SerDes/PHY IP
- Familiarity with PCIe Gen 6/7 and Ethernet standards
- Experience in coverage analysis and closure
- Ability to work with analogue/mixed-signal designs
- Strong problem-solving skills
- Leadership and mentoring capabilities
Benefits
- Opportunity for hands-on impact
- Collaboration with leading experts in AI
- Potential for growth in a hyper-growth company
- Engagement in cutting-edge technology development
- Inclusive work environment
Opens the official application on the employer’s site. No login required.