Physical Design Engineer

About this role

Axelera AI seeks a Physical Design Engineer to develop advanced AI compute SoCs, supporting the full ASIC design flow from synthesis through layout verification. You'll work with industry-standard EDA tools and collaborate across teams in a hybrid role based in Eindhoven.

What you'll do

• Support synthesis, place and route, timing analysis, and physical verification in ASIC design
• Perform clock tree synthesis and timing optimization tasks
• Integrate IP blocks including memories, I/Os, and embedded processors
• Operate EDA tools such as Fusion Compiler, Primetime, Calibre, and Formality
• Develop automation scripts in Python, Tcl, or Bash for design flow
• Collaborate with architecture, RTL, and verification teams to resolve design issues

What they're looking for

• ASIC physical design (RTL to GDS flow)
• EDA tool proficiency (Fusion Compiler, Primetime, Calibre)
• Timing analysis and constraint generation
• Clock tree synthesis
• Python and Tcl scripting
• IP integration and physical verification
• Problem-solving and collaboration
• English (fluent)

Benefits

• Competitive compensation package
• Pension plan and extensive employee insurance
• Company share options
• Hybrid and flexible working arrangements
• Multiple office locations across Europe
• Collaborative, innovation-focused culture