Skip to main content

E-Space

SoC Power Architecture Engineer - Processor Subsystem

Saratoga, CAfull-timemidAdded 1 month ago

About this role

E-Space is hiring a SoC Power Architecture Engineer to design power domain architectures for processor subsystems in satellite IoT applications. The role involves creating efficient power strategies for space-based connectivity solutions, focusing on aggressive duty cycling and ultra-low power consumption for LEO satellite systems.

What you'll do

  • Define and design power domain architectures for ASIC-based processor subsystems
  • Partition complex processor subsystems with optimized power strategies
  • Implement duty cycling techniques for satellite IoT end-node devices
  • Optimize standby power consumption within constrained energy budgets
  • Develop power management solutions for space-based applications
  • Collaborate on satellite IoT connectivity system architecture

What they're looking for

  • SoC and ASIC power architecture design
  • Power domain partitioning and optimization
  • Low-power circuit design
  • Duty cycling and power management strategies
  • Processor subsystem design
  • IoT and satellite systems knowledge
  • Energy budget analysis
  • Hardware design experience
Apply with Autofill

Opens the application — the Jobs AI extension fills it for you. Set up autofill

Opens the official application on the employer’s site. No login required.

E-Space

E-Space builds LEO satellite constellations and ground infrastructure for global IoT and wireless communications, with advanced solar power systems. The company is hiring across manufacturing engineering, wireless systems validation, modem software development, network protocols, and specialized materials engineering roles.

View all jobs at E-Space

Likely interview questions

  • Describe your experience designing power domain architectures for ASICs. How do you approach partitioning power domains to optimize for both active and standby power consumption?
  • Tell us about a time you worked on duty cycling strategies for power-constrained devices. What trade-offs did you consider between performance, latency, and energy efficiency?