Normalcomputing
Design Verification Engineer
- Confirmed live in the last 24 hours
- $0.2k–$400k
- Mid level
- Full-time
- Remote · New York City
- 5+ yrs exp
- Added 2 months ago
About this role
Normal Computing is seeking a Design Verification Engineer to ensure the quality and functionality of their unique ASICs and contribute to the refinement of their AI-powered verification tools. This role involves hands-on verification, defining data quality standards, and occasionally supporting customer deployments, applying your deep verification expertise to novel silicon and AI-driven workflows.
What you'll do
- Verify internal ASICs through testbench creation, assertions, and coverage analysis.
- Review and improve AI-generated verification collateral.
- Define and maintain data quality standards for verification training data.
- Provide support during customer deployments, validating AI-generated collateral.
- Evaluate and implement EDA tools.
What they're looking for
- SystemVerilog
- UVM methodology
- vManager
- Xcelium
- Jasper
- Python
- Perl
- Digital Verification
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Normalcomputing
Likely interview questions
- Describe your experience with UVM methodology and how you've used it in previous verification projects.
- How have you used Python or Perl scripting to automate verification tasks?