RTL & Co-design Engineer (junior)

About this role

OpenAI seeks a junior RTL engineer to design compute, memory, and interconnect components for custom AI accelerators. You'll translate AI workloads into efficient hardware by collaborating across architecture, verification, and ML teams in a hands-on role with significant ownership from concept to silicon.

What you'll do

• Write production-quality microarchitecture and RTL for accelerator subsystems
• Conduct architectural studies including performance modeling and feasibility analysis
• Collaborate with software, simulator, and compiler teams on hardware/software co-design
• Partner with design verification and physical design teams to meet functional, timing, and power targets
• Build and review performance and functional models to validate design intent
• Support design reviews, documentation, and silicon bring-up across the full lifecycle

What they're looking for

• Verilog/SystemVerilog RTL design
• Computer architecture
• AI/ML hardware accelerator design
• Hardware modeling and simulation
• Design tools (lint, CDC/RDC, synthesis, STA)
• Hardware/software co-design
• Cross-functional collaboration
• Performance analysis and optimization

Benefits

• Hybrid work model (3 days on-site per week in San Francisco)
• Relocation assistance available
• Work on cutting-edge AI-native silicon technology
• Collaborate with world-class architecture and ML teams