RTL & Codesign Engineer

About this role

OpenAI seeks an RTL & Codesign Engineer to design compute, memory, and interconnect components for custom AI accelerators. You'll translate AI workloads into efficient hardware by collaborating across architecture, verification, and software teams while owning the full design lifecycle from definition through silicon bring-up.

What you'll do

• Design and implement production-quality RTL for major accelerator subsystems (compute, memory, interconnect)
• Perform architectural studies including performance modeling and feasibility analysis for AI workloads
• Collaborate with software, compiler, and simulator teams on hardware-software co-design
• Partner with design verification and physical design teams to meet timing, area, power, and functional targets
• Build and validate performance and functional models to confirm design intent
• Support design reviews, documentation, and silicon bring-up across the full lifecycle

What they're looking for

• RTL design in Verilog/SystemVerilog with production tape-out experience
• Computer architecture and AI/ML hardware-software co-design
• Hardware modeling and architectural simulator development
• Industry design tools (lint, CDC/RDC, synthesis, STA)
• Cross-functional collaboration with architecture, ML, compiler, and verification teams
• Performance modeling and workload analysis
• Problem-solving across algorithm to circuit abstraction layers
• High-performance compute or accelerator system experience

Benefits

• Work on next-generation AI-native silicon at scale
• Hybrid work model (3 days in office per week)
• Based in San Francisco, CA with relocation assistance