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SambaNova Systems

Physical Design Methodology & Flow Engineer

San Jose, California, United StatesFrom $255kmidAdded 1 month ago

About this role

SambaNova Systems seeks an experienced Physical Design Flow Developer to own and develop RTL-to-GDS flow solutions using Cadence tools for advanced AI chip design. You'll collaborate with physical designers and tool vendors to optimize design flows for cutting-edge TSMC technology nodes.

What you'll do

  • Develop and maintain physical design composition flow using Cadence tools (Genus, Innovus, Cerebrus)
  • Troubleshoot and resolve physical design and flow issues in collaboration with design teams
  • Engage with tool vendors to identify and address tool bugs and implement flow enhancements
  • Ensure RTL-to-GDS flow methodology compliance across advanced technology nodes
  • Create and optimize scripting solutions for design automation and flow efficiency
  • Mentor physical designers on flow best practices and tool utilization

What they're looking for

  • RTL-to-GDS flow and methodology (synthesis, place and route)
  • Cadence physical design tools (Genus, Innovus, Cerebrus)
  • Advanced scripting (TCL, Perl, Python)
  • Physical design rules for sub-3nm TSMC technology nodes
  • Cadence reference flow and methodologies
  • AI/ML tools (Claude) for flow optimization
  • Design for manufacturability (DFM) principles
  • Chip design fundamentals and optimization techniques
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SambaNova Systems

SambaNova Systems builds AI inference and machine learning platforms with specialized compiler infrastructure and runtime optimization. The company is hiring for compiler engineers, software engineers, runtime engineers, and ML solutions engineers to enhance its AI platform capabilities, as well as process and quality engineers for manufacturing excellence.

Website
sambanova.ai
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Likely interview questions

  • Describe your experience with complete RTL-to-GDS flows and the specific tools you've used; what were the most complex challenges you resolved?
  • How have you optimized physical design flows to meet timing, power, and area constraints on advanced technology nodes?
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