SpaceX
AMS Verification Engineer (RFIC Engineering)
About this role
SpaceX seeks an AMS Verification Engineer to develop verification flows and testbenches for next-generation RFICs and RF-SoCs powering Starlink's satellite and ground infrastructure. You'll collaborate with cross-functional teams to create behavioral models, run simulations, and validate critical mixed-signal interfaces for space-deployed connectivity systems.
What you'll do
- Develop analog-on-top and digital-on-top verification flows for full-chip RFIC and RF-SoC simulations
- Create testbenches and flows to validate interfaces between RFICs and SoCs
- Collaborate with designers to optimize speed and accuracy of mixed-signal IP simulations (PLLs, DACs, ADCs)
- Build behavioral models for RF/analog/mixed-mode circuit blocks in Verilog-A/AMS
- Partner with ATE test engineering to develop and prototype testplans
- Execute EM/IR simulations for chip validation
What they're looking for
- AMS simulation tools and flows
- System-Verilog and UVM
- Verilog-A/AMS behavioral modeling
- Python programming
- Analog circuit fundamentals (LDOs, bandgaps, DACs, ADCs, PLL, RF amplifiers)
- Digital circuit design and RTL/gate-level netlists
- Annotated gate-level simulation
- IC design and verification methodologies
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SpaceX
SpaceX develops advanced spacecraft and satellite systems, including the Starshield government satellite constellation and Starfall re-entry cargo capsule for global delivery. The company is hiring engineers in avionics integration, software test automation, mechanical design, and hardware reliability to validate flight-critical systems and ensure mission success.
- Website
- spacex.com
Likely interview questions
- Describe your experience developing verification flows for mixed-signal integrated circuits—what tools and methodologies have you used?
- How have you approached modeling analog circuit blocks like PLLs or DACs, and what challenges did you encounter?