Tensordyne
Mid Level ASIC Design Engineer
- Confirmed live in the last 24 hours
- No salary listed
- Mid level
- On-site · Sunnyvale, CA
- 3+ yrs exp
- Added 2 months ago
About this role
Tensordyne is seeking a Mid-Level ASIC Design Engineer to join their team and contribute to the microarchitecture and implementation of high-performance AI ASICs. This role involves defining microarchitectures, integrating third-party IP, and collaborating with various engineering teams to ensure design quality and timing closure. If you're a self-starter with a passion for AI and a strong background in ASIC design, this is an exciting opportunity to shape the future of AI inference acceleration.
What you'll do
- Reconciling architectural changes with microarchitecture
- Defining and documenting microarchitecture
- Selecting and integrating third-party IP blocks
- Collaborating with design verification engineers
- Analyzing frontend synthesis and addressing issues
- Providing guidance to backend teams on place-and-route and timing closure
Benefits
- Health and financial security benefits
- Flexible spending
- Bonusly awards
- Supportive work environment
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Tensordyne
Likely interview questions
- Describe your experience with RTL logic design for multi-million gate ASICs.
- Explain your familiarity with ARM/RISC-V/MIPS architectures and cache coherency.