Physical Design/CAD Engineer

About this role

Astera Labs seeks a Physical Design/CAD Engineer to lead RTL-to-GDS ownership for connectivity ASIC designs, managing synthesis, place-and-route, timing, and signoff across complex chips for major cloud and networking customers. The role combines EDA flow development, physical design execution, and cross-functional collaboration to achieve optimal performance, power, and area in advanced semiconductor nodes.

What you'll do

• Support and build EDA tool flows for physical design across synthesis, place-and-route, extraction, and signoff stages
• Drive physical design activities ensuring robust signoff for complex SoCs and subsystems
• Architect flow improvements and enhance backend design methodology for high-performance results
• Define requirements with cross-functional teams to achieve best power, performance, and area (PPA)
• Own block-level partitions through closure including place-and-route, timing analysis, and design rule checks
• Partner with design, implementation, and verification teams to drive convergence and provide signoff expertise

What they're looking for

• Place-and-route (PnR) and full-chip timing closure
• Cadence and/or Synopsys EDA tool proficiency
• Advanced node design (7nm or below)
• Scripting in Tcl, Python, or Perl
• Extraction, formal verification, and DRC/LVS expertise
• Physical design flow development and methodology
• Cross-functional collaboration and independent problem-solving
• High-speed digital design concepts

Benefits

• Competitive base salary range: $135K–$165K (Senior) or $160K–$195K (Staff)
• Opportunity to work on AI infrastructure for leading hyperscalers
• Fully on-site role in San Jose with established technical teams
• Potential ownership of design blocks from implementation through signoff
• Professional development in cutting-edge semiconductor connectivity technologies
• Inclusive workplace culture welcoming diverse backgrounds and experiences