Design Verification Engineer - Interface IP

About this role

Etched seeks a Design Verification Engineer to own verification of Interface IP subsystems (PCIe, Ethernet, CPU, peripherals) for AI inference hardware. You'll develop UVM-based testbenches, validate vendor IP integration, and drive coverage closure across complex hardware-software interactions.

What you'll do

• Own end-to-end verification of IP subsystems including PCIe, Ethernet, CPU architectures, and low-power peripherals
• Develop and maintain UVM/SystemVerilog verification environments for functional correctness and performance validation
• Manage vendor IP configurations and coordinate with internal teams on IP handoff and integration
• Collaborate with SoC and integration DV teams to validate IP interaction within the broader chip architecture
• Drive coverage closure by defining metrics, analyzing gaps, and testing corner cases and stress scenarios
• Validate seamless hardware-software stack interaction across prefill and decode workloads

What they're looking for

• Design verification (5+ years)
• SystemVerilog and UVM
• PCIe, Ethernet, AXI/AMBA, ARM/ARC CPU protocols
• Testbench development and reusable verification methodologies
• Vendor IP integration and third-party VIP handling
• Cross-functional collaboration with RTL, software, and emulation teams
• Coverage analysis and sign-off
• Corner-case bug detection and creative problem-solving

Benefits

• Medical, dental, and vision coverage with $500/month credit for waiving medical
• Wellness benefits including fitness and mental health
• Daily lunch and dinner in office
• Unlimited compute budget subject to ROI justification