Lumilens

Design Engineer

San JosefulltimemidAdded today

About this role

Design and implement high-speed digital RTL for the front-end datapath of a chip, connecting UCIe and optical interfaces. You'll own blocks from micro-architecture through verification, writing clean, timing-aware SystemVerilog while collaborating across architecture, DV, and backend teams.

What you'll do

Develop block-level micro-architecture and RTL implementation in SystemVerilog for datapath, adapters, and FIFOs
Write lint-clean, CDC/RDC-clean RTL following coding standards and manage clock-gating and pipelining for power/timing
Create block-level testbenches, SVA assertions, and sanity checks before handing off to design verification
Integrate IP blocks, support parameterization, and ensure blocks meet configurability requirements
Partner with backend team on timing closure, synthesis, and physical design of assigned blocks
Support bring-up, debug, and silicon validation across simulation, emulation, and FPGA prototyping environments

What they're looking for

SystemVerilog RTL design (3+ years)
Digital design fundamentals: pipelining, FSMs, FIFOs, CDC, streaming interfaces
Lint and CDC/RDC compliance; clean RTL practices
Power and timing analysis; synthesis and timing closure
SVA assertion-based verification
Python, Perl, or TCL scripting for debug and automation
High-speed datapath or interface design (UCIe, PCIe preferred)
Simulation debug and waveform analysis

Likely interview questions

Walk us through a datapath block you designed from micro-architecture to verification—how did you handle timing closure and power constraints?
Describe your experience with clock-domain crossing and CDC verification. What tools and methodologies have you used?

Tell us about a time you debugged a complex RTL issue in simulation. What was your approach, and what scripting did you use?
Have you worked with high-speed interfaces like UCIe, PCIe, or similar? What were the key design challenges?
How do you approach writing clean, lint-free RTL? What coding standards and practices do you follow?
Describe your experience with assertion-based verification (SVA) and block-level testbenches. How do you ensure adequate coverage?
Tell us about your collaboration with backend teams on timing and physical closure. What metrics or constraints do you focus on?

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