Verification Engineer

About this role

Lumilens seeks a Verification Engineer to build UVM testbenches and drive functional verification for a novel photonic chiplet powering AI supercomputing. You'll verify complex blocks and subsystems through simulation and emulation, collaborating with design and architecture teams to achieve coverage closure.

What you'll do

• Develop and extend UVM testbenches with agents, sequences, and scoreboards for assigned blocks
• Write directed and constrained-random tests with functional and code coverage to closure
• Verify photonic engines against algorithmic golden models with error injection scenarios
• Integrate and run VIP-based compliance tests (UCIe, link-training, lane-repair)
• Perform register verification (UVM RAL), firmware co-simulation, and mixed-signal verification
• Support hardware-assisted verification on emulation and FPGA prototyping platforms

What they're looking for

• UVM and SystemVerilog
• Constrained-random and coverage-driven verification
• Testbench development and coverage closure
• Python, Perl, or TCL scripting
• Simulation debugging and failure triage
• CI/regression flows
• High-speed SerDes or PAM4 verification (preferred)
• Mixed-signal verification (preferred)

Benefits

• Work on first-of-its-kind photonics infrastructure for AI computing
• Well-funded startup backed by Mayfield
• Collaborate with world-class engineers solving hard optical and systems challenges
• Ground-floor opportunity to shape tomorrow's computing infrastructure
• Hands-on role with opportunity to expand scope as chip and team mature

Likely interview questions

• Walk us through your experience building a UVM testbench from scratch—what challenges did you face and how did you drive coverage to closure?
• Describe a time you debugged a complex failure across simulation that required collaboration with the design team. How did you approach it?