Neuralink
Digital Verification Engineer
South San Francisco, California, United StatesFrom $243kfull-timemidAdded today
About this role
Neuralink seeks an experienced ASIC Design Verification Engineer to develop and validate digital modules for brain-computer interface implants, focusing on high-throughput, low-power digital signal processing within their System-on-Chip team.
What you'll do
- Develop and execute comprehensive verification strategies for complex ASIC designs
- Write and maintain SystemVerilog testbenches and verification automation scripts
- Design and implement code coverage and regression testing frameworks
- Collaborate on SoC architecture verification from RTL through physical design
- Debug and validate low-power and functional simulation flows
- Support lab bring-up, diagnostic development, and system-level debugging
What they're looking for
- SystemVerilog
- ASIC verification and design
- Python, Perl, Tcl, shell scripting
- UVM verification methodology
- Formal verification
- ARM/RISC-V processors and AMBA bus protocols
- Low-power design and power-aware verification
- FPGA/emulation and SystemC/C++
Benefits
- Equity compensation (RSUs) for full-time employees
- Medical, dental, and vision insurance (PPO)
- Paid holidays and flexible time off
- Commuter benefits and on-site meals
- 401(k) retirement plan
- Parental leave and career advancement opportunities
Opens the application — the Jobs AI extension fills it for you. Set up autofill
Opens the official application on the employer’s site. No login required.
Neuralink
Neuralink develops brain-computer interface technology and neurosurgical robots to enable direct interaction between the brain and computing systems. The company is hiring engineers across clinical implementation, user interface design, manufacturing, and software development to support its pioneering medical devices and surgical systems.
- Website
- neuralink.com
Likely interview questions
- Describe your experience developing automated verification flows and regression suites for digital ASIC designs.
- Walk us through a complex SoC verification challenge you faced and how you debugged and resolved it.