3D Stacked DRAM-on-Logic Design Engineer

About this role

SK hynix America seeks a 3D Stacked DRAM-on-Logic Design Engineer in San Jose to lead digital IP design for next-generation 3D-stacked DRAM solutions, collaborating closely with U.S. customers and foundry partners to deliver optimized DRAM-on-Logic configurations. This role is central to strengthening the company's competitive position in advanced memory technology.

What you'll do

• Design and develop digital IP for 3D-stacked DRAM to enable DRAM-on-Logic system configurations
• Lead RTL design and implementation of memory PHY and hard macro IP for high-speed circuits
• Collaborate with foundry companies to build and validate 3D-stacked DRAM digital IP
• Engage directly with U.S.-based customers to align technical solutions with their requirements
• Conduct PPA analysis and optimization with focus on physical design implementation
• Implement memory BIST, DFT, and DFD features for robust design

What they're looking for

• RTL design using Verilog or VHDL
• Memory PHY and high-speed digital IP design
• Memory controller architecture and implementation
• Memory BIST, DFT, and DFD methodologies
• PPA analysis and physical design optimization
• 3D DRAM and stacked memory technologies
• Cross-functional technical communication
• SoC and digital logic IP development

Benefits

• Top-tier health insurance at no employee cost
• PTO, company holidays, and happy Fridays
• Paid parental leave program
• 401k matching
• Educational reimbursement up to $10,000 annually
• Free meals and corporate discount programs