SpaceX
Design Verification Engineer (Silicon Engineering)
Irvine, CA$125k–$145kmidAdded today
About this role
SpaceX seeks a Design Verification Engineer to develop and validate next-generation ASICs for Starlink satellites and ground infrastructure. You'll create comprehensive testbenches, execute verification plans, and ensure silicon quality from pre-silicon through post-silicon validation.
What you'll do
- Perform digital ASIC verification at block and system levels
- Write and review test plans, develop test harnesses and sequences
- Build SystemVerilog testbench infrastructure using UVM and non-UVM methodologies
- Execute test plans, run regressions, and achieve code and functional coverage closure
- Automate test case generation using Python and MATLAB
- Support pre-silicon verification, chip bring-up, and post-silicon validation activities
What they're looking for
- SystemVerilog testbench development
- UVM verification methodology
- Python scripting and automation
- MATLAB programming
- Constrained random verification
- RTL design understanding
- Test plan development and coverage analysis
- Object-oriented programming
Benefits
- Comprehensive medical, vision, and dental coverage
- 401(k) retirement plan
- Company stock and equity options
- 3 weeks paid vacation plus 10+ paid holidays
- Short and long-term disability insurance
- Paid parental leave
Opens the official application on the employer’s site. No login required.
SpaceX
SpaceX develops advanced spacecraft and satellite systems, including the Starshield government satellite constellation and Starfall re-entry cargo capsule for global delivery. The company is hiring engineers in avionics integration, software test automation, mechanical design, and hardware reliability to validate flight-critical systems and ensure mission success.
- Website
- spacex.com
Likely interview questions
- Describe your experience developing SystemVerilog testbenches—have you used both UVM and non-UVM approaches, and which do you prefer?
- Walk us through how you've achieved functional coverage closure on a complex design; what challenges did you face?