SpaceX
Design Verification Engineer (Silicon Engineering)
About this role
SpaceX seeks a Design Verification Engineer to develop and validate next-generation ASICs for Starlink satellites and ground infrastructure. You'll create comprehensive test plans, SystemVerilog testbenches, and automation scripts to ensure digital designs meet performance requirements across block and system levels.
What you'll do
- Perform digital ASIC verification at block and system level
- Write and review test plans, develop test harnesses and test sequences
- Develop SystemVerilog testbench infrastructure using UVM and non-UVM methodologies
- Execute test plans, run regressions, and close code and functional coverage
- Automate test case generation using Python and MATLAB
- Support pre-silicon verification, chip bring-up, and post-silicon validation
What they're looking for
- SystemVerilog testbench development
- UVM verification methodology
- Python scripting and automation
- Test plan development and coverage analysis
- Object-oriented programming
- MATLAB
- Constrained random verification
- RTL design understanding
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SpaceX
SpaceX develops advanced spacecraft and satellite systems, including the Starshield government satellite constellation and Starfall re-entry cargo capsule for global delivery. The company is hiring engineers in avionics integration, software test automation, mechanical design, and hardware reliability to validate flight-critical systems and ensure mission success.
- Website
- spacex.com
Likely interview questions
- Describe your experience developing SystemVerilog testbenches—what methodologies have you used, and how did you ensure comprehensive coverage?
- Walk us through your approach to writing and executing a test plan for a complex digital design.