SpaceX
Design Verification Engineer (Silicon Engineering)
Palo Alto, CA$135k–$155kmidAdded today
About this role
SpaceX is hiring a Design Verification Engineer to develop and validate next-generation ASICs for Starlink satellites and ground infrastructure. You'll create testbenches, write verification plans, and ensure complex digital designs meet requirements through pre-silicon and post-silicon validation.
What you'll do
- Perform digital ASIC verification at block and system levels
- Write test plans, develop testbenches and test sequences
- Build SystemVerilog testbench infrastructure using UVM and non-UVM methodologies
- Execute test plans, run regressions, and close code and functional coverage
- Automate test case generation using Python and MATLAB
- Support pre-silicon verification, chip bring-up, and post-silicon validation
What they're looking for
- SystemVerilog and testbench development
- UVM and verification methodologies
- Python and MATLAB scripting
- Object-oriented programming
- Constrained random verification
- Test plan development and coverage analysis
- RTL design knowledge
- Problem-solving and debugging
Benefits
- Stock options and long-term cash incentives
- Comprehensive medical, vision, and dental coverage
- 401(k) retirement plan
- 3 weeks paid vacation plus 10+ paid holidays annually
- Paid parental leave and disability insurance
- Employee stock purchase plan with discount
Opens the official application on the employer’s site. No login required.
SpaceX
SpaceX develops advanced spacecraft and satellite systems, including the Starshield government satellite constellation and Starfall re-entry cargo capsule for global delivery. The company is hiring engineers in avionics integration, software test automation, mechanical design, and hardware reliability to validate flight-critical systems and ensure mission success.
- Website
- spacex.com
Likely interview questions
- Describe your experience writing SystemVerilog testbenches and which verification methodologies you've used most extensively.
- Walk us through how you've approached closing functional coverage gaps in a previous ASIC project.