RTL Design Engineer (Silicon Engineering)

About this role

SpaceX is looking for an RTL Design Engineer to develop advanced FPGAs and ASICs for its Starlink projects. The role involves engaging in full design lifecycles, from conceptual design to testing, aimed at enhancing global connectivity through innovative technology.

What you'll do

• Design ASICs and FPGAs using Verilog/SystemVerilog
• Participate in the full design lifecycle from architecture to validation
• Engage in high-level architectural design
• Collaborate with cross-functional teams to develop new technologies

What they're looking for

• Bachelor's degree in relevant engineering field
• 1+ years experience in RTL design
• Proficiency in SystemVerilog or Verilog
• ASIC/FPGA integration experience
• Familiarity with EDA tools and HDL simulators
• Knowledge of AXI/AHB/APB protocols
• Strong problem-solving skills
• Ability to work in dynamic environments

Benefits

• Competitive salary with potential for performance bonuses
• Long-term stock incentives
• Comprehensive medical, vision, and dental coverage
• 401(k) retirement plan
• Paid parental leave and vacation
• Access to employee discounts and perks