AMD Coding Interview Questions
25 AMD coding interview problems with full optimal solutions — 8 easy, 12 medium, 5 hard. Every problem ships with multiple approaches (brute-force first, then the optimal), complexity tables for each, company-specific tips on what an AMD interviewer values, and a FAQ section.
Showing 2 problems of 25
- #146mediumvery frequently asked
146. LRU Cache
Design a Least Recently Used cache with O(1) get and put. AMD asks this because cache design is central to their business — TLBs, L1/L2/L3 caches, and GPU shared-memory eviction policies all operate on LRU or LRU-like principles. Understanding the data structure composition here directly maps to hardware cache architecture reasoning.
- #191mediumvery frequently asked
191. Number of 1 Bits
Count the number of set bits (population count) in a 32-bit integer. AMD treats this as a serious bit-manipulation signal — popcount is a hardware instruction (POPCNT in x86, vcnt in ARM) that appears in GPU shader parity checks, ECC implementations, sparse-matrix compression, and bitboard game AI. Knowing the Brian Kernighan trick separates candidates who understand bits from those who don't.