AMD Coding Interview Questions
25 AMD coding interview problems with full optimal solutions — 8 easy, 12 medium, 5 hard. Every problem ships with multiple approaches (brute-force first, then the optimal), complexity tables for each, company-specific tips on what an AMD interviewer values, and a FAQ section.
Showing 12 problems of 25
- #3mediumfrequently asked
3. Longest Substring Without Repeating Characters
Find the length of the longest substring with all unique characters. AMD uses sliding-window problems to test whether candidates can maintain state efficiently across a moving window — a pattern that appears in stream processing, cache eviction, and pipeline hazard detection.
- #15mediumfrequently asked
15. 3Sum
Find all unique triplets in an array that sum to zero. AMD uses this to test whether candidates can extend a two-pointer pattern and handle deduplication without a set — skills that transfer to collision detection and register-bank conflict resolution in compiler backends.
- #49mediumfrequently asked
49. Group Anagrams
Group strings that are anagrams of each other. AMD tests this to check hash-key design — generating a canonical key from unsorted data is analogous to instruction fingerprinting and opcode normalization in compiler IR passes.
- #56mediumfrequently asked
56. Merge Intervals
Given a list of intervals, merge all overlapping ones. AMD uses this to test sorting plus linear scan — the same pattern appears in merging memory-mapped regions, coalescing DMA transfer ranges, and combining address-space reservations in driver memory management.
- #139mediumfrequently asked
139. Word Break
Determine if a string can be segmented into words from a dictionary. AMD uses this to test bottom-up DP with substring matching — the same reachability pattern applies to tokenizing instruction streams, parsing ISA assembly strings, and validating opcode sequences in a compiler front-end.
- #146mediumvery frequently asked
146. LRU Cache
Design a Least Recently Used cache with O(1) get and put. AMD asks this because cache design is central to their business — TLBs, L1/L2/L3 caches, and GPU shared-memory eviction policies all operate on LRU or LRU-like principles. Understanding the data structure composition here directly maps to hardware cache architecture reasoning.
- #191mediumvery frequently asked
191. Number of 1 Bits
Count the number of set bits (population count) in a 32-bit integer. AMD treats this as a serious bit-manipulation signal — popcount is a hardware instruction (POPCNT in x86, vcnt in ARM) that appears in GPU shader parity checks, ECC implementations, sparse-matrix compression, and bitboard game AI. Knowing the Brian Kernighan trick separates candidates who understand bits from those who don't.
- #200mediumfrequently asked
200. Number of Islands
Count the number of islands in a 2D grid. AMD uses BFS/DFS grid traversal to test whether candidates understand connected-component analysis — a pattern that maps directly to GPU texture block connectivity, render target region detection, and cluster analysis in performance heat maps.
- #207mediumfrequently asked
207. Course Schedule
Determine if you can finish all courses given a list of prerequisites. This is cycle detection in a directed graph — AMD tests it because dependency ordering is fundamental to task graph scheduling, GPU compute graph compilation, and LLVM IR pass ordering in their compiler toolchain.
- #238mediumfrequently asked
238. Product of Array Except Self
Return an array where each element is the product of all other elements, without using division and in O(n). AMD uses this to test prefix/suffix scan thinking — the same left-pass/right-pass pattern underlies SIMD prefix-sum instructions, parallel reduction, and scan primitives on GPU hardware.
- #322mediumfrequently asked
322. Coin Change
Find the minimum number of coins to make a given amount. AMD uses this unbounded-knapsack DP to test state-space minimization thinking — the same 'minimum cost to reach a target state' pattern arises in GPU instruction scheduling, power-state transitions, and DVFS (dynamic voltage and frequency scaling) optimization.
- #347mediumfrequently asked
347. Top K Frequent Elements
Return the k most frequent elements from an array. AMD asks this to probe heap vs bucket-sort trade-offs — the same decision appears when ranking the most-used GPU kernels, hottest cache lines, or most-frequent instruction patterns in a profile-guided optimization pass.