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Astera Labs

Digital RTL Design Engineer- Static Timing Analysis

San Jose, California, United StatesmidAdded today

About this role

Astera Labs seeks a Digital RTL Design Engineer specializing in Static Timing Analysis to develop synthesizable Verilog/SystemVerilog for high-performance AI and connectivity ASICs. You'll translate microarchitectural specifications into robust RTL, collaborate across verification and physical design teams, and drive designs through synthesis, timing closure, and silicon validation.

What you'll do

  • Develop synthesizable Verilog/SystemVerilog RTL for digital ASIC blocks and subsystems in connectivity products
  • Translate architectural specifications into datapaths, control logic, state machines, and protocol logic
  • Collaborate with verification engineers on test plans, functional requirements, and coverage goals
  • Debug simulation failures using waveform analysis, assertions, and root-cause analysis techniques
  • Support synthesis, static timing analysis, and timing closure activities to meet performance targets
  • Participate in design reviews and RTL quality improvements for performance, power, and area optimization

What they're looking for

  • Verilog/SystemVerilog RTL design and synthesis
  • Static timing analysis and timing closure
  • Digital design methodology and coding standards
  • Clock-domain crossing (CDC) and reset-domain crossing (RDC) techniques
  • UVM-based verification and simulation debugging
  • Logic synthesis tools and EDA flows
  • ASIC design and implementation experience
  • Collaborative problem-solving and technical communication
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Astera Labs

Astera Labs designs high-speed semiconductor connectivity solutions and ASICs for AI infrastructure, including SerDes/PHY IP and CXL Smart Memory Controllers. The company is hiring design verification engineers, quality engineers, firmware engineers, and physical design engineers to develop and validate these advanced chips for cloud and hyperscale platforms.

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Likely interview questions

  • Walk us through your experience with static timing analysis—what timing constraints have you managed and how did you approach timing closure?
  • Describe a complex RTL module you designed; how did you ensure it was synthesizable and met performance targets?
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