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Astera Labs

Formal Verification and RTL Design Software Engineer

  • Confirmed live in the last 24 hours
  • $160.5k–$200k
  • Mid level
  • On-site · San Jose, California, United States
  • 4+ yrs exp
  • Added 1 month ago

About this role

Astera Labs seeks a Software Engineer to develop AI-powered tools for accelerating RTL design and formal verification workflows. You'll leverage LLMs and agentic frameworks to assist engineers in debugging, optimizing code, and analyzing verification reports. This role requires a blend of software engineering expertise and familiarity with hardware design and verification methodologies.

What you'll do

  • Design, develop, and deploy AI applications using LLMs for RTL, physical, and analog design.
  • Build infrastructure for LLM-powered engineering assistants and dialogue systems.
  • Develop agentic AI solutions for tasks like RTL lint checking, optimization, and formal proof convergence.
  • Build and maintain design databases and dashboards to surface relevant engineering data.
  • Collaborate with RTL design, DV, formal verification, and CAD/EDA teams.

What they're looking for

  • Python
  • LLMs
  • Agentic Frameworks
  • RTL Design (Verilog/SystemVerilog)
  • Formal Verification Tools (JasperGold, VC Formal)
  • Data Structures
  • Algorithms
  • Software Engineering
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Astera Labs

Astera Labs designs high-speed semiconductor connectivity solutions and ASICs for AI infrastructure, including SerDes/PHY IP and CXL Smart Memory Controllers. The company is hiring design verification engineers, quality engineers, firmware engineers, and physical design engineers to develop and validate these advanced chips for cloud and hyperscale platforms.

Industry
Technology & Software
View all jobs at Astera Labs

Likely interview questions

  • Describe your experience fine-tuning LLMs and what metrics you used to evaluate success.
  • Explain your approach to integrating AI solutions into existing CAD/EDA workflows.
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