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Astera Labs

System Validation Engineer - All Levels (AI Fabric Switches)

San Jose, California, United States$148.5k–$240kmidAdded 2 months ago

About this role

Astera Labs seeks System Validation Engineers to lead post-silicon bring-up and validation for high-performance PCIe fabric switches powering AI data centers. You'll design validation strategies, automate test flows, investigate cross-layer issues, and collaborate with customers to certify products for rack-scale AI infrastructure.

What you'll do

  • Create comprehensive validation plans covering functionality, performance, reliability, and interoperability for AI fabric switch products
  • Lead silicon and platform bring-up activities on x86 and ARM systems, verifying boot and runtime behavior
  • Debug complex issues across PCIe, NVMe, Ethernet, firmware, and hardware layers using protocol and logic analyzers
  • Develop Python automation for IC and board testing with emphasis on test orchestration, data analysis, and reporting
  • Collaborate with customers to capture requirements, reproduce scenarios, and validate real-world product performance
  • Drive cross-functional root-cause analysis with silicon, firmware, hardware, and software teams

What they're looking for

  • Python automation for bench control and test orchestration
  • PCIe and high-speed protocol knowledge (NVMe, Ethernet, CXL)
  • Silicon and system bring-up experience
  • x86 and ARM architecture understanding
  • Protocol analyzers and logic analyzers
  • UEFI/Linux boot sequences
  • Root-cause analysis across multiple layers
  • Technical communication and customer collaboration
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Astera Labs

Astera Labs designs high-speed semiconductor connectivity solutions and ASICs for AI infrastructure, including SerDes/PHY IP and CXL Smart Memory Controllers. The company is hiring design verification engineers, quality engineers, firmware engineers, and physical design engineers to develop and validate these advanced chips for cloud and hyperscale platforms.

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Likely interview questions

  • Walk us through a complex silicon bring-up issue you debugged—what layers were involved and how did you isolate the root cause?
  • Describe your experience with PCIe protocol validation. Have you worked with PCIe compliance testing or consortium test suites?
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