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Cesium Astro

FPGA Engineer II

Austin, TXfull-timemidAdded today

About this role

CesiumAstro seeks an FPGA Engineer II to design and verify high-performance FPGA circuits for satellite and aerospace communication systems. You'll work across the full development lifecycle, from HDL design through deployment, in a dynamic startup environment focused on cutting-edge space technology.

What you'll do

  • Design and implement FPGA circuits in Verilog/VHDL for high-speed serial interfaces and digital processing
  • Develop and execute verification and validation test plans for FPGA designs
  • Manage complex multi-clock domain architectures and timing requirements
  • Characterize designs using lab instruments including oscilloscopes, spectrum analyzers, and signal generators
  • Collaborate cross-functionally across hardware and systems teams throughout development phases
  • Analyze and document worst-case performance, failure modes, and reliability metrics

What they're looking for

  • FPGA design (Verilog, VHDL, Vivado)
  • HDL simulation and verification (ModelSim or equivalent)
  • High-speed digital design and serial interfaces
  • Digital signal processing
  • RF/microwave test equipment operation
  • Timing closure and multi-clock domain design
  • Board-level hardware design
  • Technical documentation and communication

Benefits

  • Company stock options
  • Health, dental, and vision insurance
  • HSA and FSA accounts
  • Life and disability coverage
  • Retirement plans
  • Dynamic startup work environment with cross-functional collaboration
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Cesium Astro

Cesium Astro develops advanced hardware and systems for aerospace applications including satellites, UAVs, and rocket propulsion platforms. The company is hiring for specialized engineering roles including FPGA engineers, wire harness designers, turbomachinery engineers, and software project engineers to support its satellite and spacecraft development.

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Likely interview questions

  • Walk us through a complex FPGA design you've implemented—what were the key challenges with clock domains or high-speed interfaces?
  • Describe your experience verifying FPGA designs; what tools and methodologies have you used most effectively?
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