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Cesium Astro

FPGA Engineer II

El Segundo, CA$118k–$142kfull-timemidAdded yesterday

About this role

CesiumAstro seeks an FPGA Engineer II to design and verify cutting-edge hardware for satellite and aerospace communication systems. You'll develop HDL-based FPGA circuits with high-speed interfaces, digital processing cores, and multi-clock domain management, working across the full development lifecycle in a dynamic startup environment.

What you'll do

  • Design FPGA circuits and systems using Verilog/VHDL at the HDL level
  • Develop high-speed serial interfaces, digital processing cores, and clock domain management
  • Perform verification, testing, and validation of FPGA designs using industry tools
  • Conduct lab testing with oscilloscopes, spectrum analyzers, and signal analysis equipment
  • Collaborate cross-functionally on satellite and aerospace platform integration
  • Support FPGA deployment and troubleshooting throughout the development lifecycle

What they're looking for

  • FPGA design and verification (Verilog/VHDL)
  • Xilinx Vivado and ModelSim
  • High-speed serial interface design
  • Multi-clock domain and timing analysis
  • Lab instrumentation (oscilloscopes, spectrum analyzers, signal generators)
  • Digital signal processing
  • HDL coding and simulation
  • Hardware testing and validation

Benefits

  • Company stock options
  • Health, dental, and vision insurance
  • HSA and FSA accounts
  • Life and disability insurance
  • Retirement plans
  • Dynamic, collaborative startup environment
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Cesium Astro

Cesium Astro develops advanced hardware and systems for aerospace applications including satellites, UAVs, and rocket propulsion platforms. The company is hiring for specialized engineering roles including FPGA engineers, wire harness designers, turbomachinery engineers, and software project engineers to support its satellite and spacecraft development.

View all jobs at Cesium Astro

Likely interview questions

  • Describe your experience designing FPGA systems with high-speed serial interfaces and multiple clock domains—what challenges did you face and how did you resolve them?
  • Walk us through your process for verifying and validating a complex FPGA design from specification through deployment.
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