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Cesium Astro

FPGA Engineer II

Westminster, CO$113k–$136kfull-timemidAdded today

About this role

CesiumAstro is seeking an FPGA Engineer II to design and verify FPGA circuits for satellite and aerospace communication systems. You'll work across the full development lifecycle, implementing high-speed serial interfaces, digital processing cores, and complex clock domain logic in a dynamic startup environment.

What you'll do

  • Design and implement FPGA circuits using HDL (Verilog/VHDL) for high-speed serial interfaces and data streaming applications
  • Perform verification and testing of FPGA designs using tools like Modelsim and Vivado
  • Validate designs using lab instruments including oscilloscopes, spectrum analyzers, and signal generators
  • Manage multi-clock domain designs and implement management interfaces
  • Conduct worst-case analysis and reliability assessments for aerospace-qualified systems
  • Collaborate cross-functionally throughout all phases of hardware development

What they're looking for

  • FPGA design and verification (Verilog or VHDL)
  • Xilinx Vivado and ModelSim
  • High-speed serial interface design
  • Multi-clock domain design
  • Digital signal processing
  • Lab instrumentation (oscilloscopes, spectrum analyzers, RF generators)
  • Aerospace design standards
  • Failure analysis and reliability engineering

Benefits

  • Company stock options
  • Health, dental, and vision insurance
  • HSA and FSA accounts
  • Life and disability coverage
  • Retirement plans
  • Dynamic, collaborative startup environment
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Cesium Astro

Cesium Astro develops advanced hardware and systems for aerospace applications including satellites, UAVs, and rocket propulsion platforms. The company is hiring for specialized engineering roles including FPGA engineers, wire harness designers, turbomachinery engineers, and software project engineers to support its satellite and spacecraft development.

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Likely interview questions

  • Describe your experience designing and implementing high-speed serial interfaces in FPGA; what challenges did you encounter and how did you resolve them?
  • Walk us through your process for managing multiple clock domains in a single FPGA design—what synchronization techniques have you used?
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