FPGA Verification Engineer II

About this role

CesiumAstro seeks an FPGA Verification Engineer II to develop and maintain advanced UVM-based testbenches for satellite and aerospace digital systems. You'll lead verification infrastructure improvements, mentor team members, and collaborate with engineering leadership to implement cutting-edge phased array verification methodologies using SystemVerilog, DPI-C, and Xilinx tools.

What you'll do

• Design and develop UVMf-based testbenches at module and top-level with reusable components and best practices
• Build and maintain continuous integration and regression testing infrastructure for FPGA designs
• Create custom VIP modules and integrate MATLAB/Python numerical models via DPI-C interfaces
• Mentor engineers across experience levels on testbench usage and modern FPGA verification approaches
• Evaluate FPGA simulation tools including Xilinx TLM models and QEMU-RP integration
• Collaborate with vendors and leadership to define simulation requirements and implement process improvements

What they're looking for

• SystemVerilog and UVMf testbench development
• FPGA verification (VHDL, Verilog, C/C++, SystemC)
• DPI-C, TLM, Formal CDC, and functional verification analysis
• CI/CD infrastructure and regression testing
• Xilinx FPGA design tools
• Linux and scripting
• QEMU and VIP integration
• MATLAB/Python model integration

Benefits

• Stock options
• Health, dental, and vision insurance
• HSA and FSA accounts
• Life and disability insurance
• Retirement plans
• Dynamic startup environment with cross-functional collaboration