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Cesium Astro

FPGA Verification Engineer II

Austin, TXfull-timemidAdded today

About this role

CesiumAstro seeks an FPGA Verification Engineer II to design and develop advanced testbenches and verification infrastructure for phased array systems used in satellite and aerospace platforms. The role emphasizes UVMf-based testing, continuous integration, custom VIP development, and cross-functional collaboration in a dynamic startup environment.

What you'll do

  • Develop UVMf-based testbenches at module and top-level using SystemVerilog, VIP, and DPI-C integration with MATLAB and Python models
  • Design and maintain reusable custom verification IP modules following industry best practices
  • Build and enhance continuous integration and regression testing infrastructure for FPGA designs
  • Mentor engineers on UVMf testbench methodologies and modern FPGA verification approaches
  • Evaluate and integrate Xilinx TLM models and QEMU-RP simulation infrastructure
  • Collaborate with vendors on simulation model requirements and process improvements

What they're looking for

  • SystemVerilog and UVMf testbench development
  • FPGA verification (Verilog, VHDL, C/C++, SystemC)
  • DPI-C and TLM modeling
  • Xilinx FPGA tools
  • Continuous integration and regression testing
  • Linux
  • QEMU and hardware-in-the-loop testing
  • Formal verification and CDC analysis

Benefits

  • Company stock options
  • Health, dental, and vision insurance
  • HSA and FSA accounts
  • Life and disability insurance
  • Retirement plans
  • Dynamic startup environment with cross-functional collaboration
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Cesium Astro

Cesium Astro develops advanced hardware and systems for aerospace applications including satellites, UAVs, and rocket propulsion platforms. The company is hiring for specialized engineering roles including FPGA engineers, wire harness designers, turbomachinery engineers, and software project engineers to support its satellite and spacecraft development.

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Likely interview questions

  • Describe your experience developing UVMf-based testbenches and how you've approached reusability across module and top-level verification.
  • How have you integrated DPI-C interfaces between SystemVerilog and external tools like MATLAB or Python in previous projects?
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