IMC
Verification Engineer
About this role
Join IMC's R&D team as a Verification Engineer to validate cutting-edge trading systems and accelerate hardware verification processes. You'll collaborate across distributed teams to design automated testbenches and drive verification closure using advanced tools and methodologies.
What you'll do
- Develop and maintain system and block-level testbenches using UVM methodology
- Collaborate with RTL and software teams to validate complex hardware designs
- Automate verification flows and regression testing to enable rapid development cycles
- Track and report coverage metrics to drive verification closure
- Work with industry-standard EDA tools and scripting to optimize verification processes
- Contribute to forward-looking solutions that anticipate future technical requirements
What they're looking for
- UVM (Universal Verification Methodology)
- SystemVerilog and Verilog
- C++
- EDA tools (industry-standard third-party solutions)
- Scripting languages
- Regression test automation and tracking
- Linux environment
- Coverage-driven verification and metrics analysis
Benefits
- Discretionary bonus eligibility
- Paid leave
- Insurance coverage
- Global distributed team environment
- Exposure to cutting-edge trading technology
- Collaborative research-driven culture
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IMC
IMC builds trading technology and financial systems powered by software, machine learning, and hardware engineering. The company is hiring interns and graduate-level engineers and researchers across software, machine learning, and hardware disciplines to develop trading algorithms, research strategies, and collaborative technology solutions.
View all jobs at IMCLikely interview questions
- Walk us through your experience building UVM testbenches—what was the most complex design you've verified and how did you approach it?
- How have you used coverage metrics to identify and close verification gaps in your previous roles?