Lightmatter

Hardware Verification Engineer — Electro-Optic Links

Boston, MAFrom $250kmidAdded today

About this role

Lead hardware verification and characterization of high-speed electro-optic links for Lightmatter's photonics-based AI data center infrastructure. You'll own verification methodology, drive bench testing of novel optical-electrical systems, build predictive models, and mentor senior engineers while solving critical signal integrity challenges across silicon and system programs.

What you'll do

Conduct hands-on lab characterization and debug of high-speed electro-optic hardware with novel failure modes
Build and validate system-level electrical/optical/EO channel models against bench measurements
Own link budget and verification methodology while executing measurements and correlations
Characterize eye diagrams, BER, jitter, equalization, and channel impairments across 56G+ serial links
Support silicon bring-up and root-cause analysis with analog, package, PCB, and SerDes teams
Develop automation and tools to accelerate characterization workflows and mentor engineers

What they're looking for

High-speed serial links (56G/112G/224G+) and SerDes equalization (CTLE/FFE/DFE)
Signal integrity, S-parameters, crosstalk analysis, and link budget modeling
Lab instrumentation: VNA, oscilloscopes, BERTs, TDRs
Simulation and modeling tools: ADS, HFSS, Cadence, COMSOL, COM/IBIS-AMI
Python and MATLAB for automation frameworks
Silicon photonics and electro-optic systems architecture
Package/PCB/channel co-design
Team mentoring and technical leadership

Benefits

Competitive base salary ($195,000–$250,000) plus equity grants
Comprehensive medical, dental, and vision coverage
401(k) matching and life insurance
Generous paid time off, sick leave, and paid family leave
Flexible hybrid work model in Boston, MA
Professional development and training programs

Likely interview questions

Walk us through a high-speed link failure you debugged that stalled others—what was your methodology and what did you discover?
How have you built and validated channel models in past projects, and how did you ensure correlation with hardware measurements?

Describe your experience with SerDes equalization techniques (CTLE/FFE/DFE)—which have you optimized and for what data rates?
Tell us about a time you influenced chip or system architecture based on bench findings—what tradeoffs did you uncover?
How do you approach mentoring senior or staff-level engineers while maintaining deep hands-on lab involvement yourself?
What automation or tools have you built to accelerate characterization workflows, and what languages did you use?
Have you worked with silicon photonics or electro-optic systems before, and if so, what unique verification challenges did you encounter?

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