SambaNova Systems
Design Verification Engineer
About this role
SambaNova Systems seeks a Design Verification Engineer to develop and execute verification for chip-level control and initialization features on the RDU AI processor. You'll create SystemVerilog/UVM environments to verify complex sequencing, state transitions, and cross-subsystem interactions, collaborating closely with architects, RTL designers, and firmware teams.
What you'll do
- Develop and execute verification plans for chip-level control and initialization features
- Build SystemVerilog/UVM verification environments with test sequences, checkers, assertions, and functional coverage
- Verify sequencing, dependencies, state transitions, and recovery scenarios across multiple chip subsystems
- Create directed and constrained-random tests to identify corner cases
- Debug simulation and regression failures, root-cause issues with design teams
- Analyze coverage metrics and drive verification to closure
What they're looking for
- SystemVerilog and UVM
- Constrained-random verification and functional coverage
- Assertion-based verification
- Chip initialization, control sequencing, and clocking
- Python, Perl, TCL, or shell scripting
- Simulation debug and problem-solving
- Digital design and SoC architecture
- CDC/RDC verification (preferred)
Opens the official application on the employer’s site. No login required.
SambaNova Systems
SambaNova Systems builds AI inference and machine learning platforms with specialized compiler infrastructure and runtime optimization. The company is hiring for compiler engineers, software engineers, runtime engineers, and ML solutions engineers to enhance its AI platform capabilities, as well as process and quality engineers for manufacturing excellence.
- Website
- sambanova.ai
Likely interview questions
- Describe your experience developing UVM verification environments for complex chip-level features; what challenges did you encounter?
- Walk us through how you've approached verifying state transitions and sequencing across multiple subsystems in a previous project.