Physical Design Engineer (Silicon Engineering)

About this role

SpaceX seeks a Physical Design Engineer to develop next-generation ASICs for Starlink satellite and ground infrastructure systems. You'll execute the complete RTL-to-GDSII flow, collaborate with cross-functional teams, and optimize chip performance for global connectivity.

What you'll do

• Execute synthesis, floorplanning, place-and-route, and signoff closure (timing, noise, power, verification)
• Develop and enhance physical design methodologies and automation scripts
• Partner with ASIC designers on feasibility studies, timing/power/area targets, and design tradeoffs
• Debug and resolve timing, congestion, and flow issues throughout implementation
• Run and close STA, noise, DRC, LVS, electromigration, and voltage drop signoff checks

What they're looking for

• RTL2GDSII physical design flow
• EDA tools (Cadence, Synopsys, Mentor Graphics)
• Static timing analysis and noise analysis
• Deep submicron FinFET process technology
• Scripting (Python, Tcl, Perl, Bash, Makefile)
• CMOS digital design and standard cell libraries
• Physical verification (DRC, LVS, DFM)
• Power analysis and optimization

Benefits

• Comprehensive medical, vision, and dental coverage
• 401(k) retirement plan with company match eligibility
• 3 weeks paid vacation and 10+ paid holidays annually
• Stock options and employee stock purchase plan
• Paid parental leave and disability insurance
• Short and long-term incentive programs