Physical Design Engineer (Silicon Engineering)

About this role

SpaceX seeks a Physical Design Engineer to develop next-generation ASICs for Starlink satellites and ground infrastructure. You'll execute the complete RTL-to-GDSII flow, collaborate with cross-functional teams, and optimize chip designs for deployment in space environments.

What you'll do

• Execute synthesis, floorplanning, place-and-route, and signoff closure (timing, power, noise, physical verification)
• Develop and improve physical design methodologies and automation scripts
• Partner with ASIC design teams on feasibility studies, timing/power/area targets, and RTL tradeoffs
• Troubleshoot and resolve design congestion, timing violations, and flow issues
• Debug and fix signoff closure issues in STA, noise analysis, equivalency checking, and electromigration verification

What they're looking for

• RTL-to-GDSII physical design flow
• EDA tools (Cadence, Synopsys, Mentor Graphics)
• Static timing analysis (STA) and timing closure
• Floorplanning, place-and-route, and power delivery
• Scripting languages (Python, Perl, TCL, bash)
• Deep submicron FinFET and CMOS design principles
• Physical verification and electromigration analysis
• DFT, scan insertion, and MBIST concepts