SpaceX
Signal Integrity Engineer - Serdes, Satellites (Starlink)
About this role
SpaceX seeks a Signal Integrity Engineer for Starlink's satellite payload systems, responsible for designing and verifying high-speed SERDES, memory interfaces, and optical communication channels throughout the product lifecycle. This role bridges electrical, mechanical, thermal, and RF disciplines, requiring expertise in advanced channel design, simulation, and troubleshooting of cutting-edge satellite hardware.
What you'll do
- Design, simulate, verify, and troubleshoot SI aspects of SERDES (10–112+ Gbps) and high-speed memory interfaces (DDR4, LPDDR5, GPDDR6, etc.)
- Architect channel transitions from die bump to die bump and derive PCB material specifications
- Collaborate cross-functionally with RF, ASIC, packaging, mechanical, thermal, and software engineers on novel product architectures
- Root cause and resolve manufacturing, test, and integration issues in PCB and satellite systems
- Define best practices, simulation workflows, test methodologies, and signoff criteria for Starlink payload SI
- Drive characterization, qualification, and debug across all phases of hardware product lifecycle
What they're looking for
- High-speed digital channel design and SERDES (56–224 Gbps)
- 3D EM simulation tools (CST, HFSS, ADS) and channel simulators
- Memory interface design (DDR4, LPDDR5, GPDDR6, QSPI, eMMC)
- Wireline transceiver concepts and DSP-based architecture
- PCB layout, stackup design, and low-loss laminate selection
- Programming (Python, C/C++) for automation and analysis
- EMI/EMC debugging and signal integrity troubleshooting
- Cross-functional hardware product development from concept to production
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SpaceX
SpaceX develops advanced spacecraft and satellite systems, including the Starshield government satellite constellation and Starfall re-entry cargo capsule for global delivery. The company is hiring engineers in avionics integration, software test automation, mechanical design, and hardware reliability to validate flight-critical systems and ensure mission success.
- Website
- spacex.com
Likely interview questions
- Walk us through your experience designing or debugging a high-speed SERDES interface above 56 Gbps—what were the key SI challenges and how did you address them?
- Describe your approach to selecting PCB materials and stackup design for a memory interface like DDR5 or GPDDR6.