Physical Design Engineer, Timing

About this role

Tenstorrent seeks a mid- to senior-level Physical Design Engineer specializing in static timing analysis to drive timing convergence on advanced-node, multi-million-gate AI chip designs through final signoff and tapeout. You'll own STA methodology, constraint development, and timing closure while collaborating across Design, DFT, and cross-functional teams in a hybrid role.

What you'll do

• Drive timing convergence across design blocks, partitions, and top-level implementations; generate and validate timing models
• Analyze timing violations, develop fixes, and debug timing-flow issues to maintain execution momentum toward tapeout
• Develop and validate bottom-up SDC constraints in partnership with Design and DFT teams
• Create engineering change orders (ECOs) and timing closure strategies for worst-case corner analysis
• Automate and improve timing workflows using Python, Perl, and Tcl scripting
• Partner with cross-functional teams on methodology updates and advanced-node design requirements

What they're looking for

• Static timing analysis (STA) and timing closure on advanced process nodes
• SDC constraint writing and debugging
• Timing flows, clocking, CDC, RDC, derates, guardbanding, and signoff methodology
• Python, Perl, and Tcl scripting for flow automation
• SPICE, place-and-route (PNR), placement, CTS, routing, and post-route optimization
• DFT integration and AI-based automation (preferred)
• Cross-functional collaboration and technical communication
• Design hierarchy and multi-level constraint propagation

Benefits

• Competitive compensation package (base + variable)
• Exposure to cutting-edge AI semiconductor technology and RISC-V CPU development
• Learn scalable timing modeling and constraints across design hierarchy
• Opportunity to shape implementation and signoff workflows with emerging AI-enabled solutions
• Hybrid work arrangement across Austin TX, Fort Collins CO, or Santa Clara CA
• Collaborative environment solving hard problems in high-performance computing