AMD Coding Interview Questions
25 AMD coding interview problems with full optimal solutions — 8 easy, 12 medium, 5 hard. Every problem ships with multiple approaches (brute-force first, then the optimal), complexity tables for each, company-specific tips on what an AMD interviewer values, and a FAQ section.
- #1easyvery frequently asked
1. Two Sum
Given an array of integers and a target, return the indices of two numbers that add up to the target. AMD interviewers use this as a warm-up that checks whether you default to the O(n^2) brute force or immediately reach for a hash map to get O(n).
- #3mediumfrequently asked
3. Longest Substring Without Repeating Characters
Find the length of the longest substring with all unique characters. AMD uses sliding-window problems to test whether candidates can maintain state efficiently across a moving window — a pattern that appears in stream processing, cache eviction, and pipeline hazard detection.
- #4hardoccasionally asked
4. Median of Two Sorted Arrays
Find the median of two sorted arrays in O(log(m+n)). AMD asks this as the canonical binary-search-on-two-arrays hard — the O(log n) constraint forces a partitioning insight rather than a merge. AMD engineers apply similar binary-search-based reasoning to bisecting performance bottlenecks in multi-stream profiler data.
- #15mediumfrequently asked
15. 3Sum
Find all unique triplets in an array that sum to zero. AMD uses this to test whether candidates can extend a two-pointer pattern and handle deduplication without a set — skills that transfer to collision detection and register-bank conflict resolution in compiler backends.
- #20easyfrequently asked
20. Valid Parentheses
Given a string of brackets, determine if it is valid. AMD uses this to test stack fluency — knowing when a LIFO structure is the right tool is fundamental to compiler and parser design, both core to AMD's toolchain work.
- #21easyfrequently asked
21. Merge Two Sorted Lists
Merge two sorted linked lists into one sorted list. AMD uses this to test pointer manipulation and dummy-node technique — the same pattern appears in hardware sorted-merge units, priority queues in task schedulers, and merge phases of external sort in GPU memory.
- #23hardfrequently asked
23. Merge K Sorted Lists
Merge k sorted linked lists into one sorted list. AMD uses this to test min-heap design and divide-and-conquer — both strategies appear in GPU command queue aggregation, multi-stream kernel scheduling, and external merge sort over large datasets that exceed on-chip memory.
- #42hardfrequently asked
42. Trapping Rain Water
Calculate how much water can be trapped between elevation bars. AMD uses this to test two-pointer reasoning under asymmetric constraints — the same left/right boundary propagation appears in memory range overlap analysis, voltage droop modeling, and signal amplitude clipping detection in hardware bring-up tooling.
- #49mediumfrequently asked
49. Group Anagrams
Group strings that are anagrams of each other. AMD tests this to check hash-key design — generating a canonical key from unsorted data is analogous to instruction fingerprinting and opcode normalization in compiler IR passes.
- #53easyfrequently asked
53. Maximum Subarray
Find the contiguous subarray with the largest sum. AMD asks this to test Kadane's algorithm — a greedy single-pass technique relevant to performance profiling, where you scan a sequence of GPU frame times to find the worst sustained latency window.
- #56mediumfrequently asked
56. Merge Intervals
Given a list of intervals, merge all overlapping ones. AMD uses this to test sorting plus linear scan — the same pattern appears in merging memory-mapped regions, coalescing DMA transfer ranges, and combining address-space reservations in driver memory management.
- #70easyfrequently asked
70. Climbing Stairs
Count the distinct ways to climb n stairs taking 1 or 2 steps at a time. AMD uses this classic DP entry point to check whether candidates recognize overlapping subproblems and memoize — essential thinking for optimization passes in compilers and GPU shader pipelines.
- #121easyfrequently asked
121. Best Time to Buy and Sell Stock
Find the maximum profit from a single buy-sell stock transaction. AMD tests this to check greedy single-pass thinking — the same left-to-right minimum-tracking technique applies when scanning performance counters or telemetry streams for the best baseline vs peak delta.
- #127hardoccasionally asked
127. Word Ladder
Find the shortest transformation sequence from beginWord to endWord, changing one letter at a time. AMD uses BFS shortest-path problems to test graph modeling — the same one-step-change-at-a-time traversal appears in ISA mutation analysis, hardware configuration space search, and register file allocation in compiler backends.
- #136easyfrequently asked
136. Single Number
Find the one element that appears exactly once when every other element appears twice. AMD asks this as a bit-manipulation entry point — XOR is fundamental to parity checking, error detection in memory controllers, and CRC computation in hardware data paths.
- #139mediumfrequently asked
139. Word Break
Determine if a string can be segmented into words from a dictionary. AMD uses this to test bottom-up DP with substring matching — the same reachability pattern applies to tokenizing instruction streams, parsing ISA assembly strings, and validating opcode sequences in a compiler front-end.
- #146mediumvery frequently asked
146. LRU Cache
Design a Least Recently Used cache with O(1) get and put. AMD asks this because cache design is central to their business — TLBs, L1/L2/L3 caches, and GPU shared-memory eviction policies all operate on LRU or LRU-like principles. Understanding the data structure composition here directly maps to hardware cache architecture reasoning.
- #191mediumvery frequently asked
191. Number of 1 Bits
Count the number of set bits (population count) in a 32-bit integer. AMD treats this as a serious bit-manipulation signal — popcount is a hardware instruction (POPCNT in x86, vcnt in ARM) that appears in GPU shader parity checks, ECC implementations, sparse-matrix compression, and bitboard game AI. Knowing the Brian Kernighan trick separates candidates who understand bits from those who don't.
- #200mediumfrequently asked
200. Number of Islands
Count the number of islands in a 2D grid. AMD uses BFS/DFS grid traversal to test whether candidates understand connected-component analysis — a pattern that maps directly to GPU texture block connectivity, render target region detection, and cluster analysis in performance heat maps.
- #201hardfrequently asked
201. Bitwise AND of Numbers Range
Find the bitwise AND of all numbers in the range [left, right]. AMD asks this as a pure bit-manipulation hard — the insight that AND of a range equals the common prefix of left and right in binary is directly tied to address-range masking, subnet mask computation, and MMIO region overlap detection in hardware driver code.
- #206easyfrequently asked
206. Reverse Linked List
Reverse a singly linked list in-place. AMD uses this to probe pointer manipulation — the same mental model you need when traversing hardware descriptor chains, DMA linked lists, or command ring buffers in GPU driver code.
- #207mediumfrequently asked
207. Course Schedule
Determine if you can finish all courses given a list of prerequisites. This is cycle detection in a directed graph — AMD tests it because dependency ordering is fundamental to task graph scheduling, GPU compute graph compilation, and LLVM IR pass ordering in their compiler toolchain.
- #238mediumfrequently asked
238. Product of Array Except Self
Return an array where each element is the product of all other elements, without using division and in O(n). AMD uses this to test prefix/suffix scan thinking — the same left-pass/right-pass pattern underlies SIMD prefix-sum instructions, parallel reduction, and scan primitives on GPU hardware.
- #322mediumfrequently asked
322. Coin Change
Find the minimum number of coins to make a given amount. AMD uses this unbounded-knapsack DP to test state-space minimization thinking — the same 'minimum cost to reach a target state' pattern arises in GPU instruction scheduling, power-state transitions, and DVFS (dynamic voltage and frequency scaling) optimization.
- #347mediumfrequently asked
347. Top K Frequent Elements
Return the k most frequent elements from an array. AMD asks this to probe heap vs bucket-sort trade-offs — the same decision appears when ranking the most-used GPU kernels, hottest cache lines, or most-frequent instruction patterns in a profile-guided optimization pass.