Astera Labs
Product Application Engineer PCIe/CXL
About this role
Astera Labs seeks a Principal Product Application Engineer to provide technical leadership for PCIe/CXL semiconductor design-ins in the China region. You'll drive customer technical solutions, debug complex system issues across silicon/firmware/hardware layers, and coordinate with internal teams—working afternoons/evenings PST to align with Asia Pacific stakeholders.
What you'll do
- Guide customers through PCIe/CXL design challenges and silicon bring-up, debugging at physical layer and system level
- Lead troubleshooting of multi-layer issues involving silicon, firmware, board design, and system environment
- Generate technical collateral and documentation for existing and new connectivity products
- Direct internal teams and drive communication across customer, FAE, and sales stakeholders toward issue resolution
- Provide product feedback and innovation insights to engineering and product teams
- Support regional customers during 12 PM–9 PM PST working hours to enable real-time Asia Pacific collaboration
What they're looking for
- PCIe protocol and physical layer expertise (5.0 minimum, 6.0/CXL preferred)
- Silicon bring-up, system-level debugging, and protocol analyzer/oscilloscope/BERT equipment operation
- C firmware development and Python or equivalent scripting languages
- Data center system architecture (servers, switches, BMC, BIOS configuration)
- PCIe compliance testing and troubleshooting methodology
- Technical leadership and cross-functional communication
- Mandarin Chinese (written and spoken) for customer interaction
- Electrical engineering fundamentals and complex SoC/high-speed interface design
Benefits
- Competitive base salary $185,000–$240,000
- Discretionary bonus and incentive eligibility
- Health and benefits package
- Opportunity to shape AI infrastructure and next-generation connectivity standards
- Work with hyperscaler customers on cutting-edge semiconductor solutions
- Collaborative environment encouraging innovation and diversity
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Astera Labs
Astera Labs designs high-speed semiconductor connectivity solutions and ASICs for AI infrastructure, including SerDes/PHY IP and CXL Smart Memory Controllers. The company is hiring design verification engineers, quality engineers, firmware engineers, and physical design engineers to develop and validate these advanced chips for cloud and hyperscale platforms.
View all jobs at Astera LabsLikely interview questions
- Walk us through your most complex PCIe debugging experience—what tools did you use and how did you isolate the root cause?
- Describe a time you coordinated between a customer, internal engineering, and sales to resolve a critical design-in issue. How did you manage stakeholder communication?