Etched
Physical Design Engineer - Block Level, Subsystem Implementation
About this role
Etched seeks a Physical Design Engineer to own block-level and subsystem chip implementation from synthesis through GDSII sign-off for frontier AI inference hardware. You'll drive timing closure, power optimization, and signoff across advanced process nodes while collaborating with RTL designers to accelerate product delivery.
What you'll do
- Own end-to-end block-level physical design including floorplanning, synthesis, placement, CTS, and routing through GDSII
- Drive timing closure across all corners and modes, including constraint development and ECO implementation
- Close signoff across EM, IR drop, RC extraction, DRC, LVS, and antenna checks
- Generate abstracts, views, and timing budgets for hierarchical top-level integration
- Provide physical design feedback to RTL designers for PPA improvements
- Supervise and ensure quality of third-party physical design work
What they're looking for
- RTL-to-GDSII flow and design methodology
- Cadence Innovus/Genus or Synopsys Fusion Compiler
- Static timing analysis and sign-off tools (PrimeTime, Tempus, Voltus)
- UPF-based low power design and power verification
- Advanced process node implementation (5nm and below)
- Tcl, Python, or Perl scripting for automation
- Floorplanning, placement, routing, and CTS expertise
- IR drop and EM/antenna analysis
Benefits
- Comprehensive medical, dental, and vision coverage with generous premiums
- $500/month credit for waiving medical benefits
- $2k/month housing subsidy for those near the office
- Relocation support for San Jose moves
- Wellness benefits covering fitness and mental health
- Daily lunch and dinner in office; unlimited compute budget subject to ROI
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Etched
Etched builds AI inference hardware, designing and manufacturing complex mechanical and electrical components for data center systems. The company is hiring mechanical engineers, PCB designers, hardware verification engineers, and software engineers to develop manufacturing processes, circuit boards, verification infrastructure, and internal tools across its hardware and operations.
- Website
- etched.com
Likely interview questions
- Walk us through your most recent block-level physical design closure—what were the main timing bottlenecks and how did you resolve them?
- Describe your experience with advanced process nodes below 5nm and any unique design challenges you encountered.