Etched.ai

Power Validation Engineer

San JosefulltimemidAdded today

About this role

Etched seeks a Power Validation Engineer to characterize power consumption and delivery performance for custom AI inference chips and system platforms. You'll design measurement campaigns, validate power delivery networks, and drive findings into silicon and system design from early bring-up through production.

What you'll do

Design and execute power measurement campaigns across multiple voltage rails under LLM inference and stress workloads; characterize peak, sustained, and idle power envelopes
Validate power delivery network (PDN) performance including VRM response, PCIe compliance, and impedance; provide feedback on capacitor placement and design
Profile power transient events and correlate with performance monitor data; build automated power sweep frameworks across model configurations
Run extended stress workloads (72+ hours) to identify reliability risks and throttling behavior; manage multi-zone thermal profiling
Validate power sequencing, telemetry accuracy, and alert thresholds across cold-start, hot-restart, and fault scenarios; own pass/fail criteria for qualification stages
Debug electrical component defects and design flaws; develop automated test procedures and analyze data to support engineering decisions

What they're looking for

ASIC and system-level power delivery design (VRM, PDN, decoupling)
Precision measurement equipment (differential probes, network analyzers, oscilloscopes)
Multi-phase power converter tuning and validation
Silicon bring-up and hardware debugging
Test automation and scripting
Transient analysis and workload characterization
Power electronics and thermal profiling
Data analysis and technical reporting

Likely interview questions

Walk us through your experience designing and executing power measurement campaigns on ASICs. How did you characterize peak, sustained, and idle power across PVT corners, and how did you translate that into derating curves for system specs?
Describe a time you debugged a complex power delivery or transient issue that only surfaced under specific workload or environmental conditions. What instruments and methodology did you use to isolate root cause?

Tell us about your hands-on experience with PDN validation — how have you measured VRM load step response, PDN impedance, or PCIe power compliance, and how did you feed those findings back to PCB and package design teams?
What's your experience with silicon bring-up? Walk us through the power validation challenges you encountered and how you addressed them from first silicon through production qualification.
Have you profiled power transient events and correlated them with on-die performance monitor data? How would you build an automated power sweep framework that exercises inference workloads across model sizes, batch sizes, sequence lengths, and precision modes?
Describe your experience running extended stress workloads (72+ hours) to surface reliability and thermal issues. How do you instrument multi-zone thermal profiles and communicate findings to cross-functional teams?
Tell us about a time you owned the complete power sequencing validation, PMBus telemetry accuracy, and alert threshold testing across cold-start, hot-restart, and fault-injection scenarios. How did you define pass/fail criteria?

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