MatX
Silicon Validation Engineer
About this role
MatX seeks a Silicon Validation Engineer to own chip bring-up and validation for AGI compute hardware, from first power-on through production readiness. You'll develop validation plans, execute high-stress workloads, debug complex cross-functional failures, and drive silicon quality across compute, memory, and interconnect systems.
What you'll do
- Own silicon bring-up and validation activities from first power-on through feature validation, characterization, and production readiness
- Develop and execute validation plans for chip-level and SiP-level functionality, performance, reliability, and system behavior
- Debug complex failures using registers, logs, traces, waveforms, firmware output, and lab equipment across RTL, firmware, software, and silicon boundaries
- Create and execute high-stress workloads that exercise bandwidth, latency, concurrency, coherency, and error handling
- Collaborate with architecture, design, DV, firmware, and software teams to reproduce issues and drive root-cause investigations
- Develop test infrastructure, automation, and data-analysis tools to improve validation execution and failure triage
What they're looking for
- Silicon validation and post-silicon bring-up
- SoC architecture and hardware-firmware interactions
- Debug tools: registers, traces, waveforms, protocol analyzers, and lab equipment
- Python scripting and test automation
- C/C++ code reading for embedded systems
- Hardware emulation platforms (Palladium preferred)
- Validation planning and coverage definition
- Cross-functional problem-solving and ownership
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MatX
MatX builds cutting-edge AI silicon and the system software stack to power it, focusing on optimizing hardware and software for large-scale machine learning workloads. The company is hiring system software engineers, kernel developers, compiler engineers, hardware simulators, and SOC integration engineers to design high-performance AI compute platforms.
View all jobs at MatXLikely interview questions
- Walk us through your most complex silicon debug experience—what tools and methodologies did you use to isolate the root cause?
- How have you coordinated validation activities across pre-silicon (simulation, emulation) and post-silicon environments to shift validation left?