OpenAI
Design Verification Engineer
About this role
OpenAI is seeking a Design Verification Engineer to ensure functional correctness of custom AI accelerator silicon, from individual IP blocks through full SoC designs. You'll develop comprehensive testbenches and verification methodologies while collaborating with architecture, RTL, and systems teams to deliver production-grade hardware.
What you'll do
- Own verification of custom IP blocks, subsystems, or full-chip SoC functionality
- Define verification plans aligned with architecture and microarchitecture specifications
- Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM
- Build stimulus generators, checkers, monitors, and scoreboards for coverage and correctness
- Perform bug triage, root cause analysis, and collaborate on design resolution
- Maintain regression infrastructure and drive coverage closure at block and top-level
What they're looking for
- SystemVerilog and UVM
- Simulation and debug tools (VCS, Questa, Verdi)
- Computer architecture (memory, cache, coherency, interconnects)
- ML compute primitives
- Hardware verification methodology
- Formal verification or emulation (plus)
- Performance modeling (plus)
- Cross-functional collaboration
Opens the application — the Jobs AI extension fills it for you. Set up autofill
Opens the official application on the employer’s site. No login required.
OpenAI
OpenAI builds AI infrastructure and products, including large-scale data center campuses for AI computing and generative AI applications for enterprise customers. The company is hiring civil engineers, project engineers, electrical design engineers, data center R&D engineers, and AI deployment engineers to expand its infrastructure capabilities and help customers deploy AI solutions.
View all jobs at OpenAILikely interview questions
- Walk us through your experience verifying complex IP blocks or SoCs. What was the most challenging design you've verified, and how did you approach coverage closure?
- Describe your proficiency with SystemVerilog and UVM. Can you give an example of a testbench you built and how you structured your constrained-random stimulus?