openai
Design Verification Engineer
San Francisco (Remote)fulltimemid
About this role
OpenAI is seeking a Design Verification Engineer to ensure functional correctness of custom AI accelerator silicon, from individual IP blocks through full SoC designs. You'll develop comprehensive testbenches and verification methodologies while collaborating with architecture, RTL, and systems teams to deliver production-grade hardware.
What you'll do
- Own verification of custom IP blocks, subsystems, or full-chip SoC functionality
- Define verification plans aligned with architecture and microarchitecture specifications
- Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM
- Build stimulus generators, checkers, monitors, and scoreboards for coverage and correctness
- Perform bug triage, root cause analysis, and collaborate on design resolution
- Maintain regression infrastructure and drive coverage closure at block and top-level
What they're looking for
- SystemVerilog and UVM
- Simulation and debug tools (VCS, Questa, Verdi)
- Computer architecture (memory, cache, coherency, interconnects)
- ML compute primitives
- Hardware verification methodology
- Formal verification or emulation (plus)
- Performance modeling (plus)
- Cross-functional collaboration
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