RTL Design Engineer – Interconnect & Network Datapath

About this role

OpenAI's Hardware organization is seeking a senior RTL design engineer to own the microarchitecture and implementation of critical on-chip and off-chip communication systems for a custom AI accelerator. You'll design packet-based interconnects, NoCs, switches, and networking protocols while managing junior engineers and collaborating across architecture, verification, and physical design teams.

What you'll do

• Design and own microarchitecture and RTL for interconnect fabrics, routers, switches, arbiters, queues, schedulers, and traffic-management logic
• Develop on-chip and off-chip interfaces, protocol bridges, and custom networking protocols for scale-up and scale-out systems
• Perform hands-on SystemVerilog coding, simulation, and microarchitecture work from requirements through silicon bring-up
• Collaborate with architecture and performance teams to optimize latency, bandwidth, and utilization under realistic AI workloads
• Work with verification teams on coverage plans, assertions, and stress scenarios for concurrent packet behavior
• Provide technical leadership through design reviews, mentoring, and development of reusable RTL methodologies

What they're looking for

• SystemVerilog and production RTL design
• Packet-switched interconnect and networking (Ethernet, NIC, SmartNIC, RDMA/RoCE, InfiniBand)
• Queuing, arbitration, scheduling, flow control, and congestion management
• On-chip and chip-to-chip interface design (AXI, CHI, CXL, PCIe, Ethernet)
• RTL signoff flows (lint, CDC/RDC, synthesis, formal verification, STA)
• Collaboration with verification, physical design, and post-silicon teams
• NoC design and custom protocol development
• Performance analysis and optimization under workload constraints