Anduril Industries
Digital Design Engineer, Air Dominance and Strike
About this role
Anduril Industries seeks an FPGA Design Engineer to develop RTL for high-performance embedded systems and avionics supporting autonomous air platforms. You'll handle the complete design lifecycle from requirements and microarchitecture through RTL implementation, simulation, synthesis, and flight integration in a mission-critical defense environment.
What you'll do
- Design and implement RTL in VHDL, Verilog, or SystemVerilog for FPGA and SoC-based systems
- Translate system and hardware requirements into microarchitecture, interface definitions, and implementation plans
- Perform simulation, synthesis, timing closure, and lab bring-up of FPGA designs
- Integrate RTL components into high-performance embedded and avionics systems
- Support system integration and flight test of mission-critical hardware
- Collaborate across hardware, software, and mission autonomy teams on end-to-end development
What they're looking for
- FPGA/SoC RTL design (VHDL, Verilog, SystemVerilog)
- Digital logic and microarchitecture design
- Simulation and verification tools
- Synthesis and timing closure
- Embedded systems and avionics knowledge
- Hardware integration and lab troubleshooting
- Complex digital hardware design
- System requirements analysis
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Anduril Industries
Anduril Industries builds autonomous defense systems including underwater vehicles, unmanned aircraft, and electronic warfare platforms for the Department of Defense. The company is hiring across mechanical engineering, mission operations, software development, technical leadership, and advanced manufacturing roles to support the design, deployment, and production of these mission-critical systems.
- Website
- anduril.com
Likely interview questions
- Walk us through a complex RTL design you've implemented—what were the key microarchitecture decisions and how did you handle timing closure?
- Describe your experience with simulation and verification tools; how do you ensure RTL correctness before synthesis?