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Astera Labs

Fabric Modeling and Analysis Engineer for Scale Up Fabric

San Jose, California, United States$207k–$230kmidAdded today

About this role

Astera Labs seeks a Fabric Modeling and Analysis Engineer to develop performance models for the Scorpio Scale-Up Fabric, predicting bandwidth, latency, and throughput behavior under AI/ML workloads before silicon production. You'll be the internal authority on fabric modeling, influencing architectural decisions and product roadmaps through simulation and analysis.

What you'll do

  • Develop and maintain performance models for the Scorpio fabric architecture
  • Quantify bandwidth, latency, and throughput limitations under realistic AI/ML workloads
  • Predict hardware behavior and identify bottlenecks before tape-out
  • Support architectural decisions through simulation and performance analysis
  • Translate modeling insights into product roadmap and IP recommendations
  • Collaborate with architecture and design teams on scale-up fabric optimization

What they're looking for

  • Performance modeling and simulation
  • System architecture and bandwidth/latency analysis
  • AI/ML infrastructure and workload characterization
  • Python or C++ for model development
  • Interconnect or fabric design knowledge
  • Data analysis and visualization
  • Technical communication and documentation
  • Hardware-software co-design experience
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Astera Labs

Astera Labs designs high-speed semiconductor connectivity solutions and ASICs for AI infrastructure, including SerDes/PHY IP and CXL Smart Memory Controllers. The company is hiring design verification engineers, quality engineers, firmware engineers, and physical design engineers to develop and validate these advanced chips for cloud and hyperscale platforms.

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Likely interview questions

  • Walk us through how you would build a performance model for a new interconnect fabric from scratch.
  • Describe your experience modeling latency and throughput bottlenecks in complex systems.
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