Test Engineer

About this role

A mid-level Test Engineer role at a fabless semiconductor startup, responsible for owning the complete test lifecycle from DFT strategy and ATPG pattern generation through ATE bringup, OSAT coordination, and production test across multiple chip programs.

What you'll do

• Define and execute DFT strategy, generating and validating ATPG patterns including scan, MBIST, JTAG, and embedded memory sequences
• Develop and debug test programs on Advantest and Teradyne ATE platforms, supporting first silicon bringup and characterization across voltage, temperature, and frequency corners
• Serve as primary interface between internal hardware engineers and external foundry, OSAT, and test partners for test program handoff and coordination
• Track yield data from probe and final test, analyze anomalies, and drive corrective actions with suppliers
• Own test engineering across multiple active chip programs simultaneously while building scalable test infrastructure for future products
• Support load board bringup, define test flows, optimize test time, and coordinate die traceability and OTP programming in production

What they're looking for

• DFT methodology (scan insertion, ATPG, MBIST, JTAG boundary scan)
• STIL pattern generation and validation
• ATE test program development (Advantest, Teradyne)
• First silicon bringup and characterization
• Power sequencing and test mode initialization
• OSAT and supplier coordination
• Yield analysis and data-driven problem solving
• Cross-functional communication and documentation