Design Verification Engineer - Interface IP

About this role

Etched seeks a Design Verification Engineer to own verification of interface IP subsystems (PCIe, Ethernet, CPU) for their AI inference hardware. You'll develop UVM-based testbenches, collaborate across teams, and drive coverage closure to ensure architectural requirements are met in a fast-paced startup environment.

What you'll do

• Own end-to-end verification of IP subsystems including PCIe, Ethernet, CPU, and low-power peripherals
• Develop and maintain UVM/SystemVerilog verification environments for functional correctness and performance validation
• Manage vendor IP configurations and coordinate handshakes between vendor and internal IP teams
• Collaborate with integration and SoC DV teams to validate IP interactions within the chip architecture
• Drive coverage closure by defining metrics, analyzing gaps, and testing corner cases and stress scenarios

What they're looking for

• Design verification with 5+ years experience
• SystemVerilog/UVM and testbench development
• PCIe, Ethernet, AXI/AMBA, and ARM/ARC CPU protocols
• Vendor IP integration and management
• Coverage analysis and metrics definition
• Cross-functional collaboration and technical communication
• Corner-case debugging and problem-solving
• Fast-paced environment adaptability

Benefits

• Medical, dental, and vision coverage with $500/month credit option
• $2,000 per month housing subsidy for local residents
• Relocation support to San Jose
• Wellness benefits including fitness and mental health
• Daily lunch and dinner provided
• Unlimited compute budget subject to ROI justification