DFT (Design For Test) Engineer

About this role

Etched is seeking an experienced DFT Engineer to design and implement comprehensive test architectures for high-performance inference chips. You'll ensure robust testability from design through production, collaborating across teams to optimize test coverage, yield, and product quality in a cutting-edge AI hardware environment.

What you'll do

• Develop DFT architectures for ASIC/SoC designs including scan insertion, BIST, and memory testing
• Collaborate with design and verification teams to integrate testability requirements early in the design cycle
• Analyze test results and silicon debug data to improve coverage, yield, and reliability
• Create and execute DFT verification plans using simulation and formal verification techniques
• Support silicon bring-up, debug, and failure analysis during post-silicon validation
• Partner with test engineering and manufacturing teams to optimize ATE programs and test strategies

What they're looking for

• Design For Test (DFT) methodologies and best practices
• System Verilog and digital design verification
• EDA tools (Synopsys DFT Compiler, Cadence Encounter Test, Mentor Tessent)
• Scripting languages (Python, Perl, TCL)
• Scan insertion, BIST, and Memory BIST implementation
• Silicon debug and failure analysis
• JTAG and IEEE standards (1149.1, 1500)
• Mixed-signal DFT and yield analysis

Benefits

• Medical, dental, and vision coverage with generous premium support